View CY7C056V-10BAC_1507531.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

3.3v 16k/32k x 36 flex36? asynchronous dual-port static ram cy7c056v cy7c057v preliminary cypress semiconductor corporation 3901 north first street san jose ca 95134 408-943-2600 april 27, 2000 1 features ? true dual-ported memory cells which allow simulta- neous access of the same memory location 16k x 36 organization (cy7c056v) 32k x 36 organization (cy7c057v) 0.25-micron cmos for optimum speed/power high-speed access: 10/12/15/20 ns low operating power ? active: i cc = 260 ma (typical) ? standby: i sb3 = 10 a (typical) fully asynchronous operation automatic power-down expandable data bus to 72 bits or more using mas- ter/slave chip select when using more than one device on-chip arbitration logic semaphores included to permit software handshaking between ports int flag for port-to-port communication byte select on left port bus matching on right port depth expansion via dual chip enables pin select for master or slave commercial and industrial temperature ranges compact package ? 144-pin tqfp (20 x 20 x 1.4 mm) ? 172-ball bga (1.0 mm pitch) (15 x 15 x .51 mm) notes: 1. a 0 ?a 13 for 16k; a 0 ?a 14 for 32k devices. 2. busy is an output in master mode and an input in slave mode. r/w l ce 0l ce 1l oe l i/o control address decode busy l ce l interrupt semaphore arbitration sem l int l m/s r/w r ce 0r ce 1r oe r ce r logic block diagram a 0l ?a 13/14l true dual-ported ram array busy r sem r int r address decode a 0r ?a 13/14r [2] [2] [1] [1] 14/15 14/15 14/15 14/15 left port control logic i/o 18l ?i/o 26l 9 i/o 27l ?i/o 35l 9 i/o 0l ?i/o 8l 9 i/o 9l ?i/o 17l 9 right port control logic i/o control 9 9 i/o r 9 9 bus match 9/18/36 ba bm size wa b 0 ?b 3 for the most recent information, visit the cypress web site at www.cypress.com
cy7c056v cy7c057v 2 preliminary functional description the cy7c056v and cy7c057v are low-power cmos 16k and 32k x 36 dual-port static rams. various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. two ports are provided, permitting independent, asynchronous ac- cess for reads and writes to any location in memory. the de- vices can be utilized as standalone 36-bit dual-port static rams or multiple devices can be combined in order to function as a 72-bit or wider master/slave dual-port static ram. an m/s pin is provided for implementing 72-bit or wider memory appli- cations without the need for separate master and slave devic- es or additional discrete logic. application areas include inter- processor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. each port has independent control pins: chip enable (ce ) [3] , read or write enable (r/w ), and output enable (oe ). two flags are provided on each port (busy and int ). busy sig- nals that the port is trying to access the same location currently being accessed by the other port. the interrupt flag (int ) per- mits communication between ports or systems by means of a mail box. the semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. the semaphore logic is comprised of eight shared latches. only one side can control the latch (semaphore) at any time. control of a semaphore indicates that a shared re- source is in use. an automatic power-down feature is con- trolled independently on each port by chip select (ce 0 and ce 1 ) pins. the cy7c056v and cy7c057v are available in 144-pin thin quad plastic flatpack (tqfp) and 172-ball ball grid array (bga) packages. note: 3. ce is low when ce 0 v il and ce 1 v ih .
cy7c056v cy7c057v 3 preliminary pin configurations notes: 4. this pin is a14l for cy7c057v. 5. this pin is a14r for cy7c057v. 144-pin thin quad flatpack (tqfp) top view i/o32l i/o33r i/o23l i/o33l 2 3 4 i/o34l i/o34r 5 i/o35l i/o35r 6 a0l a0r 7 a1l a1r 8 a2l a2r 9 a3l a3r 10 a4l a4r 11 a5l a5r 12 a6l a6r 13 a7l 108 a7r 14 b0 107 bm 15 b1 106 size 16 b2 105 wa 17 b3 104 ba 18 oel 103 oer 19 r/wl 102 r/wr 20 vdd 101 vdd 21 vss 100 vss 22 vss 99 vdd 23 ce0l 98 ce0r 24 ce1l 97 ce1r 25 m/s 96 vdd 26 seml 95 semr 27 intl 94 intr 28 busyl 93 busyr 29 a8l 92 a8r 30 a9l 91 a9r 31 a10l 90 a10r 32 a11l 89 a11r 33 a12l 88 a12r 34 a13l 87 a13r 35 nc 86 nc 36 i/o26l 85 i/o26r i/o25l 84 i/o25r i/o24l 83 i/o24r 82 81 41 42 43 44 i/o22l i/o31l 45 vss vss 46 i/o21l i/o30l 47 i/o20l i/o29l 48 i/o19l i/o28l 49 i/o18l i/o27l 50 vdd vdd 51 i/o8l i/o17l 52 i/o7l i/o16l 53 i/o6l i/o15l 54 i/o5l i/o14l 55 vss vss 56 i/o4l i/o13l 57 i/o3l i/o12l 58 i/o2l 143 i/o11l 59 i/o1l 142 i/o10l 60 i/o0l 141 i/o9l 61 i/o0r 140 i/o9r 62 i/o1r 139 i/o10r 63 i/o2r 138 i/o11r 64 i/o3r 137 i/o12r 65 i/o4r 136 i/o13r 66 vss 135 vss 67 i/o5r 134 i/o14r 68 i/o6r 133 i/o15r 69 i/o7r 132 i/o16r 70 i/o8r 131 i/o17r 71 vdd 130 vdd 72 i/o18r 129 i/o27r 123 i/o19r 128 i/o28r 122 i/o20r 127 i/o29r 121 i/o21r 126 i/o30r 120 vss 125 vss 119 i/o22r 124 i/o31r 118 i/o23r i/o32r 117 116 37 38 39 40 80 79 78 77 76 75 74 73 115 114 113 112 111 110 109 144 1 cy7c056v (16k x 36) cy7c057v (32k x 36) [4] [5]
cy7c056v cy7c057v 4 preliminary pin configurations (continued) 172-ball ball grid array (bga) top view 1 2 3 4 567891011121314 a i/o32l i/o30l nc vss i/o13l vdd i/o11l i/o11r vdd i/o13r vss nc i/o30r i/o32r b a0l i/o33l i/o29 i/o17l i/o14l i/o12l i/o9l i/o9r i/o12r i/o14r i/o17r i/o29r i/o33r a0r c nc a1l i/o31l i/o27l nc i/o15l i/o10l i/o10r i/o15r nc i/o27r i/o31r a1r nc d a2l a3l i/o35l i/o34l i/o28l i/o16l vss vss i/o16r i/o28r i/o34r i/o35r a3r a2r e a4l a5l nc b0l nc nc nc nc bm nc a5r a4r f vdd a6l a7l b1l nc nc size a7r a6r vdd g oel b2l b3l ce0l ce0r ba wa oer h vss r/w l a8l ce1l ce1r a8r r/w rvss j a9l a10l vss m/s nc nc vdd vdd a10r a9r k a11l a12l nc seml nc nc nc nc semr nc a12r a11r l busyl a13l intl i/o26l i/o25l i/o19l vss vss i/o19r i/o25r i/o26r intr a13r busyr m nc nc i/o22l i/o18l nc i/o7l i/o2l i/o2r i/o7r nc i/o18r i/o22r nc nc n i/o24l i/o20l i/o8l i/o6l i/o5l i/o3l i/o0l i/o0r i/3r i/o5r i/o6r i/o8r i/o20r i/o24r p i/o23l i/o21l nc vss i/o4l vdd i/o1l i/o1r vdd i/o4r vss nc i/o21r i/o23r [5] [4]
cy7c056v cy7c057v 5 preliminary maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with power applied ............................................. ? 55 c to +125 c supply voltage to ground potential ............... ? 0.5v to +4.6v dc voltage applied to outputs in high z state ........................... ? 0.5v to v dd +0.5v dc input voltage ................................... ? 0.5v to v dd +0.5v [6] output current into outputs (low) ............................. 20 ma static discharge voltage .......................................... >2001v latch-up current.................................................... >200 ma shaded areas contain advance information. note: 6. pulse width < 20 ns. selection guide cy7c056v cy7c057v -10 cy7c056v cy7c057v -12 cy7c056v cy7c057v -15 cy7c056v cy7c057v -20 maximum access time (ns) 10 12 15 20 typical operating current (ma) 260 250 240 230 typical standby current for i sb1 (ma) (both ports ttl level) 60 55 50 45 typical standby current for i sb3 ( a) (both ports cmos level) 10 a10 a 10 a 10 a pin definitions left port right port description a 0l ? a 13/14l a 0r ? a 13/14r address (a 0 ? a 13 for 16k; a 0 ? a 14 for 32k devices) sem l sem r semaphore enable ce 0l , ce 1l ce 0r , ce 1r chip enable (ce is low when ce 0 v il and ce 1 v ih ) int l int r interrupt flag busy l busy r busy flag i/o 0l ? i/o 35l i/o 0r ? i/o 35r data bus input/output oe l oe r output enable r/w l r/w r read/write enable b 0 ? b 3 byte select inputs. asserting these signals enables read and write oper- ations to the corresponding bytes of the memory array. bm, size see bus matching for details. wa, ba see bus matching for details. m/s master or slave select v ss ground v dd power operating range range ambient temperature v dd commercial 0 c to +70 c 3.3v 165 mv industrial ? 40 c to +85 c 3.3v 165 mv
cy7c056v cy7c057v 6 preliminary shaded areas contain advance information. notes: 7. cross levels are v dd ? 0.2v< v z < 0.2v. 8. deselection for a port occurs if ce 0 is high or if ce 1 is low. 9. f max = 1/t rc = all inputs cycling at f = 1/t rc (except output enable). f = 0 means no address or control lines change. this applies only to inputs at cmos level standby i sb3 . 10. tested initially and after any design or process changes that may affect these parameters. electrical characteristics over the operating range [7, 8] parameter description cy7c056v cy7c057v unit -10 -12 -15 -20 min. typ. max. min. typ. max. min. typ. max. min. typ. max. v oh output high voltage (v dd = min., i oh = ? 4.0 ma) 2.4 2.4 2.4 2.4 v v ol output low voltage (v dd = min., i ol = +4.0 ma) 0.4 0.4 0.4 0.4 v v ih input high voltage 2.0 2.0 2.0 2.0 v v il input low voltage 0.8 0.8 0.8 0.8 v i oz output leakage current -10 10 ? 10 10 ? 10 10 ? 10 10 a i cc operating current (v dd = max., i out = 0 ma) outputs disabled com ? l. 260 410 250 385 240 360 230 340 ma indust. 265 385 ma i sb1 standby current (both ports ttl level and deselected) f = f max com ? l. 60 80 55 75 50 70 45 65 ma indust. 65 95 ma i sb2 standby current (one port ttl level and deselected) f = f max com ? l. 185 250 180 240 175 230 165 210 ma indust. 190 255 ma i sb3 standby current (both ports cmos level and deselect- ed) f =0 com ? l. 0.01 1 0.01 1 0.01 1 0.01 1 ma indust. 0.01 1 ma i sb4 standby current (one port cmos level and deselect- ed) f = f max [9] com ? l. 170 220 160 210 155 200 145 180 ma indust. 170 215 ma capacitance [10] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 3.3v 10 pf c out output capacitance 10 pf
cy7c056v cy7c057v 7 preliminary notes: 11. external ac test load capacitance = 10 pf. 12. (internal i/o pad capacitance = 10 pf) + ac test load. ac test load and waveforms v th =1.5v output c (a) normal load (load 1) r = 50 ? z 0 = 50 ? [11] 3.0v v ss 90% 90% 10% 3ns 3 ns 10% all input pulses 3.3v output c = 5 pf (b) three-state delay (load 2) r2 = 435 ? r1 = 590 ? (b) load derating curve 1 2 3 4 5 6 7 30 60 80 100 200 ? (ns) for access time capacitance (pf) 20 [12]
cy7c056v cy7c057v 8 preliminary switching characteristics over the operating range [13] parameter description cy7c056v cy7c057v unit -10 -12 -15 -20 min. max. min. max. min. max. min. max. read cycle t rc read cycle time 10 12 15 20 ns t aa address to data valid 10 12 15 20 ns t oha output hold from address change 33 3 3 ns t ace [3, 14] ce low to data valid 10 12 15 20 ns t doe oe low to data valid 6 8 10 12 ns t lzoe [3, 15, 16, 17] oe low to low z 0 0 0 0 ns t hzoe [3, 15, 16, 17] oe high to high z 8 10 10 12 ns t lzce [3, 13, 16, 17] ce low to low z 3 3 3 3 ns t hzce [3, 15, 16, 17] ce high to high z 8 10 10 12 ns t lzbe byte enable to low z 3 3 3 3 ns t hzbe byte enable to high z 8 10 10 12 ns t pu [3, 17] ce low to power-up 0 0 0 0 ns t pd [3, 17] ce high to power-down 10 12 15 20 ns t abe [14] byte enable access time 10 12 15 20 ns write cycle t wc write cycle time 10 12 15 20 ns t sce [3, 14] ce low to write end 7.5 10 12 15 ns t aw address valid to write end 7.5 10 12 15 ns t ha address hold from write end 00 0 0 ns t sa [14] address set-up to write start 00 0 0 ns t pwe write pulse width 7.5 10 12 15 ns t sd data set-up to write end 7.5 10 10 15 ns t hd data hold from write end 0 0 0 0 ns t hzwe [16, 17] r/w low to high z 8 10 10 12 ns t lzwe [16, 17] r/w high to low z 3 3 3 3 ns t wdd [18] write pulse to data delay 20 25 30 45 ns t ddd [18] write data valid to read data valid 16 20 25 30 ns busy timing [19] t bla busy low from address match 10 12 15 20 ns t bha busy high from address mismatch 10 12 15 20 ns t blc busy low from ce low 10 12 15 20 ns notes: 13. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3 .0v, and output loading of the specified i oi /i oh and 10-pf load capacitance. 14. to access ram, ce = l and sem = h. to access semaphore, ce = h and sem = l. either condition must be valid for the entire t sce time. 15. at any given temperature and voltage condition for any given device, t hzce is less than t lzce and t hzoe is less than t lzoe . 16. test conditions used are load 2. 17. this parameter is guaranteed by design, but it is not production tested. for information on port-to-port delay through ram c ells from writing port to reading port, refer to read timing with busy waveform. 18. for information on port-to-port delay through ram cells from writing port to reading port, refer to read timing with busy wa veform. 19. test conditions used are load 1.
cy7c056v cy7c057v 9 preliminary data retention mode the cy7c056v and cy7c057v are designed with battery backup in mind. data retention voltage and supply current are guaranteed over temperature. the following rules ensure data retention: 1. chip enable (ce ) [3] must be held high during data retention, within v dd to v dd ? 0.2v. 2. ce must be kept between v dd ? 0.2v and 70% of v dd during the power-up and power-down transitions. 3. the ram can begin operation >t rc after v dd reaches the minimum operating voltage (3.15 volts). notes: 20. t bdd is a calculated parameter and is the greater of t wdd ? t pwe (actual) or t ddd ? t sd (actual). 21. ce = v dd , v in = v ss to v dd , t a = 25 c. this parameter is guaranteed but not tested. busy timing [19] t bhc busy high from ce high 10 12 15 20 ns t ps port set-up for priority 5 5 5 5 ns t wb r/w low after busy (slave) 0 0 0 0 ns t wh r/w high after busy high (slave) 811 13 15 ns t bdd [19] busy high to data valid 10 12 15 20 ns interrupt timing [19] t ins int set time 10 12 15 20 ns t inr int reset time 10 12 15 20 ns semaphore timing t sop sem flag update pulse (oe or sem ) 10 10 10 10 ns t swrd sem flag write to read time 55 5 5 ns t sps sem flag contention win- dow 55 5 5 ns t saa sem address access time 10 12 15 20 ns switching characteristics over the operating range [13] (continued) parameter description cy7c056v cy7c057v unit -10 -12 -15 -20 min. max. min. max. min. max. min. max. timing parameter test conditions [21] max. unit icc dr1 @ vdd dr = 2v 50 a data retention mode 3.15v 3.15v v cc > 2.0v v cc to v cc ? 0.2v v cc ce t rc v ih
cy7c056v cy7c057v 10 preliminary switching waveforms notes: 22. r/w is high for read cycles. 23. device is continuously selected. ce 0 = v il , ce 1 =v ih , and b 0 , b 1 , b 2 , b 3 , wa, ba are valid. this waveform cannot be used for semaphore reads. 24. oe = v il . 25. address valid prior to or coinciding with ce 0 transition low and ce 1 transition high. 26. to access ram, ce 0 = v il , ce 1 =v ih , b 0 , b 1 , b 2 , b 3 , wa, ba are valid, and sem = v ih . to access semaphore, ce 0 = v ih , ce 1 =v il and sem = v il or ce 0 and sem =v il , and ce 1 = b 0 = b 1 = b 2 = b 3 , =v ih . t rc t aa t oha data valid previous data valid data out address t oha read cycle no. 1 (either port address access) [22, 23, 24] t ace t lzoe t doe t hzoe t hzce data valid t lzce t pu t pd i sb i cc data out b 2 , b 3 , wa, ba ce 0 , ce 1 , b 0 , b 1 , current read cycle no. 2 (either port ce /oe access) [22, 25, 26] select valid oe data out t rc address t aa t oha ce 0 , ce 1 t lzce t abe t hzce t hzce t ace t lzce read cycle no. 3 (either port) [22, 24, 25, 26] b 0 , b 1 , b 2 , b 3 , wa, ba byte select valid chip select valid
cy7c056v cy7c057v 11 preliminary notes: 27. r/w must be high during all address transitions. 28. a write occurs during the overlap (t sce or t pwe ) of ce 0 =v il and ce 1 =v ih or sem =v il and b 0 ? 3 low. 29. t ha is measured from the earlier of ce 0 /ce 1 or r/w or (sem or r/w ) going high at the end of write cycle. 30. if oe is low during a r/w controlled write cycle, the write pulse width must be the larger of t pwe or (t hzwe + t sd ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t sd . if oe is high during an r/w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t pwe . 31. to access ram, ce 0 = v il , ce 1 =sem = v ih . 32. to access byte b 0 , ce 0 = v il , b 0 = v il , ce 1 =sem = v ih . to access byte b 1 , ce 0 = v il , b 1 = v il , ce 1 =sem = v ih . to access byte b 2 , ce 0 = v il , b 2 = v il , ce 1 =sem = v ih . to access byte b 3 , ce 0 = v il , b 3 = v il , ce 1 =sem = v ih . 33. transition is measured 150 mv from steady state with a 5-pf load (including scope and jig). this parameter is sampled and n ot 100% tested. 34. during this period, the i/o pins are in the output state, and input signals must not be applied. 35. if the ce 0 low and ce 1 high or sem low transition occurs simultaneously with or after the r/w low transition, the outputs remain in the high-impedance state. switching waveforms (continued) t aw t wc t pwe t hd t sd t ha ce 0 , ce 1 r/w oe data out data in address t hzoe t sa t hzwe t lzwe write cycle no. 1: r/w controlled timing [27, 28, 29, 30] [33] [33] [30] [31, 32] note 34 note 34 chip select valid t aw t wc t sce t hd t sd t ha r/w data in address t sa write cycle no. 2: ce controlled timing [27, 28, 29, 35] ce 0 , ce 1 [31, 32] chip select valid
cy7c056v cy7c057v 12 preliminary notes: 36. ce 0 = high and ce 1 = low for the duration of the above timing (both write and read cycle). 37. i/o 0r = i/o 0l = low (request semaphore); ce 0r = ce 0l = high and ce 1r = ce 1l =low. 38. semaphores are reset (available to both ports) at cycle start. 39. if t sps is violated, the semaphore will definitely be obtained by one side or the other, but which side w ill get the semaphore is unpredictable. switching waveforms (continued) t sop t saa valid adress valid adress t hd data in va lid data out valid t oha t aw t ha t ace t sop t sce t sd t sa t pwe t swrd t doe write cycle read cycle oe r/w i/o 0 sem a 0 ? a 2 semaphore read after write timing, either side [36] match t sps a 0l ? a 2l match r/w l sem l a 0r ? a 2r r/w r sem r timing diagram of semaphore contention [37, 38, 39]
cy7c056v cy7c057v 13 preliminary note: 40. ce 0l = ce 0r = low; ce 1l = ce 1r = high. switching waveforms (continued) va lid t ddd t wdd match match r/w r data in r data outl t wc address r t pwe va lid t sd t hd address l t ps t bla t bha t bdd busy l timing diagram of write with busy (m/s =high) [40] t pwe r/w busy t wb t wh write timing with busy input (m/s =low)
cy7c056v cy7c057v 14 preliminary note: 41. if t ps is violated, the busy signal w ill be asserted on one side or the other, but there is no guarantee to which side busy will be asserted. switching waveforms (continued) address match t ps t blc t bhc address match t ps t blc t bhc ce r valid first: address l, r busy r ce 0l , ce 1l ce 0r , ce 1r busy l address l, r busy timing diagram no. 1 (ce arbitration) [41] ce l valid first: chip select valid chip select valid ce 0l , ce 1l ce 0r , ce 1r chip select valid chip select valid address match t ps address l busy r address mismatch t rc or t wc t bla t bha address r address match address mismatch t ps address l busy l t rc or t wc t bla t bha address r right address valid first: busy timing diagram no. 2 (address arbitration) [41] left address valid first:
cy7c056v cy7c057v 15 preliminary notes: 42. t ha depends on which enable pin (ce 0l /ce 1l or r/w l ) is deasserted first. 43. t ins or t inr depends on which enable pin (ce 0l /ce 1l or r/w l ) is asserted last. switching waveforms (continued) interrupt timing diagrams write 3fff (7fff for cy7c057v) t wc right side clears int r : t ha read 3fff t rc t inr write 3ffe (7ffe for cy7c057v) t wc right side sets int l : left side sets int r : left side clears int l : read 3ffe t inr t rc address l r/w l int l oe l address r r/w r int l address r r/w r int r oe r address l r/w l int r t ins t ha t ins (7fff for cy7c057v) (7fff for cy7c057v) [42] [43] [43] [43] [42] [43] ce 0l , ce 1l ce 0r , ce 1r ce 0r , ce 1r ce 0l ,ce 1l chip select valid chip select valid chip select valid chip select valid
cy7c056v cy7c057v 16 preliminary architecture the cy7c056v and cy7c057v consist of an array of 16k and 32k words of 36 bits each of dual-port ram cells, i/o and address lines, and control signals (ce 0 /ce 1 , oe , r/w ). these control pins permit independent access for reads or writes to any lo- cation in memory. to handle simultaneous writes/reads to the same location, a busy pin is provided on each port. two interrupt (int ) pins can be utilized for port-to-port communication. two semaphore (sem ) control pins are used for allocating shared resources. with the m/s pin, the devices can function as a master (busy pins are outputs) or as a slave (busy pins are inputs). the devices also have an automatic power-down fea- ture controlled by ce 0 /ce 1 . each port is provided with its own output enable control (oe ), which allows data to be read from the device. functional description write operation data must be set up for a duration of t sd before the rising edge of r/w in order to guarantee a valid write. a write operation is con- trolled by either the r/w pin (see write cycle no. 1 waveform) or the ce 0 and ce 1 pins (see write cycle no. 2 waveform). required inputs for non-contention operations are summarized in ta bl e 1 . if a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output; other- wise the data read is not deterministic. data will be valid on the port t ddd after the data is presented on the other port. read operation when reading the device, the user must assert both the oe and ce [3] pins. data will be available t ace after ce or t doe after oe is asserted. if the user wishes to access a semaphore flag, then the sem pin must be asserted instead of the ce [3] pin, and oe must also be asserted. interrupts the upper two memory locations may be used for message passing. the highest memory location (3fff for the cy7c056v, 7fff for the cy7c057v) is the mailbox for the right port and the second-highest memory location (3ffe for the cy7c056v, 7ffe for the cy7c057v) is the mailbox for the left port. when one port writes to the other port ? s mailbox, an interrupt is generated to the owner. the interrupt is reset when the owner reads the contents of the mailbox. the message is user defined. each port can read the other port ? s mailbox without resetting the interrupt. the active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. if an application does not require message passing, do not connect the interrupt pin to the processor ? s interrupt request input pin. the operation of the interrupts and their interaction with busy are summarized in table 2. busy the cy7c056v and cy7c057v provide on-chip arbitration to resolve simultaneous memory location access (contention). if both ports ? chip enables [3] are asserted and an address match occurs within t ps of each other, the busy logic will determine which port has access. if t ps is violated, one port will definitely gain permis- sion to the location, but it is not predictable which port will get that permission. busy will be asserted t bla after an address match or t blc after ce is taken low. master/slave a m/s pin is provided in order to expand the word width by configuring the device as either a master or a slave. the busy output of the master is connected to the busy input of the slave. this will allow the device to interface to a master device with no external components. writing to slave devices must be delayed until after the busy input has settled (t blc or t bla ), otherwise, the slave chip may begin a write cycle during a contention situation. when tied high, the m/s pin al- lows the device to be used as a master and, therefore, the busy line is an output. busy can then be used to send the arbitration outcome to a slave. semaphore operation the cy7c056v and cy7c057v provide eight semaphore latches, which are separate from the dual-port memory loca- tions. semaphores are used to reserve resources that are shared between the two ports. the state of the semaphore indicates that a resource is in use. for example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. the left port then verifies its success in setting the latch by reading it. after writing to the semaphore, sem or oe must be deasserted for t sop before at- tempting to read the semaphore. the semaphore value will be avail- able t swrd + t doe after the rising edge of the semaphore write. if the left port was successful (reads a 0), it assumes control of the shared resource, otherwise (reads a 1) it assumes the right port has control and continues to poll the semaphore. when the right side has relin- quished control of the semaphore (by writing a 1), the left side will succeed in gaining control of the semaphore. if the left side no longer requires the semaphore, a one is written to cancel its request. semaphores are accessed by asserting sem low. the sem pin functions as a chip select for the semaphore latches. for normal semaphore access, ce [3] must remain high during sem low. a ce active semaphore access is also available. the semaphore may be accessed through the right port with ce 0r /ce 1r active by assert- ing the bus match select (bm) pin low and asserting the bus size select (size) pin high. the semaphore may be accessed through the left port with ce 0l /ce 1l active by asserting all b 0 ? 3 byte select pins high. a 0 ? 2 represents the semaphore address. oe and r/w are used in the same manner as a normal memory access. when writing or reading a semaphore, the other address pins have no ef- fect. when writing to the semaphore, only i/o 0 is used. if a zero is written to the left port of an available semaphore, a 1 will appear at the same semaphore address on the right port. that semaphore can now only be modified by the port showing 0 (the left port in this case). if the left port now relinquishes control by writing a 1 to the sema- phore, the semaphore will be set to 1 for both ports. however, if the right port had requested the semaphore (written a 0) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. table 3 shows sample semaphore operations. when reading a semaphore, data lines 0 through 8 output the semaphore value. the read value is latched in an output reg- ister to prevent the semaphore from changing state during a write from the other port. if both ports attempt to access the semaphore within t sps of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.
cy7c056v cy7c057v 17 preliminary table 1. non-contending read/write [3] inputs outputs ce r/w oe b 0 , b 1 , b 2 , b 3 sem i/o 0 ? i/o 35 operation h x x x h high z deselected: power-down x x x all h h high z deselected: power-down l l x h/l h data in and high z write to selected bytes only l l x all l h data in write to all bytes l h l h/l h data out and high z read selected bytes only l h l all l h data out read all bytes x x h x x high z outputs disabled h h l x l data out read data in semaphore flag x h l all h l data out read data in semaphore flag h x x l data in write d in0 into semaphore flag x x all h l data in write d in0 into semaphore flag l x x any l l not allowed table 2. interrupt operation example (assumes busy l = busy r = high) [3, 44] left port right port function r/w l ce l oe l a 0 l ? 13 l int l r/w r ce r oe r a 0r ? 13r int r set right int r flag l l x 3fff x x x x x l [46] reset right int r flag x x x x x x l l 3fff h [45] set left int l flag x x x x l [45] l l x 3ffe x reset left int l flag x l l 3ffe h [46] x x x x x table 3. semaphore operation example function i/o 0 ? i/o 8 left i/o 0 ? i/o 8 right status no action 1 1 semaphore free left port writes 0 to semaphore 0 1 left port has semaphore token right port writes 0 to semaphore 0 1 no change. right side has no write access to semaphore left port writes 1 to semaphore 1 0 right port obtains semaphore token left port writes 0 to semaphore 1 0 no change. left port has no write access to semaphore right port writes 1 to semaphore 0 1 left port obtains semaphore token left port writes 1 to semaphore 1 1 semaphore free right port writes 0 to semaphore 1 0 right port has semaphore token right port writes 1 to semaphore 1 1 semaphore free left port writes 0 to semaphore 0 1 left port has semaphore token left port writes 1 to semaphore 1 1 semaphore free notes: 44. a 0l ? 14l and a 0r ? 14r , 7fff/7ffe for the cy7c057v. 45. if busy r =l, then no change. 46. if busy l =l, then no change.
cy7c056v cy7c057v 18 preliminary right port configuration [47, 48, 49] right port operation left port operation bm size configuration i/o pins used 0 0 x36 (standard) i/o 0 ? 35 0 1 x36 (ce active sem mode) i/o 0 ? 35 10x18i/o 0 ? 17 11x9i/o 0 ? 8 configuration wa ba data accessed [50] i/o pins used x36 x x dq 0 ? 35 i/o 0 ? 35 x18 0 x dq 0 ? 17 i/o 0 ? 17 x18 1 x dq 18 ? 35 i/o 0 ? 17 x9 0 0 dq 0 ? 8 i/o 0 ? 8 x9 0 1 dq 9 ? 17 i/o 0 ? 8 x9 1 0 dq 18 ? 26 i/o 0 ? 8 x9 1 1 dq 27 ? 35 i/o 0 ? 8 control pin effect b0 i/o 0 ? 8 byte control b1 i/o 9 ? 17 byte control b2 i/o 18 ? 26 byte control b3 i/o 27 ? 35 byte control notes: 47. bm and size must be configured one clock cycle before operation is guaranteed. 48. in x36 mode wa and ba pins are ? don ? t care. ? 49. in x18 mode ba pin is a ? don ? t care. ? 50. dq represents data output of the chip.
cy7c056v cy7c057v 19 preliminary bus match operation the right port of the cy7c057v 32kx36 dual-port sram can be configured in a 36-bit long-word, 18-bit word, or 9-bit byte format for data i/o. the data lines are divided into four lanes, each consisting of 9 bits (byte-size data lines). the bus match select (bm) pin works with bus size select (size) to select bus width (long-word, word, or byte) for the right port of the dual-port device. the data sequencing ar- rangement is selected using the word address (wa) and byte address (ba) input pins. a logic ? 0 ? applied to both the bus match select (bm) pin and to the bus size select (size) pin will select long-word (36-bit) operation. a logic ? 1 ? level applied to the bus match select (bm) pin will enable either byte or word bus width operation on the right port i/os depending on the logic level applied to the size pin. the level of bus match select (bm) must be static throughout device operation. normally, the bus size select (size) pin would have no stan- dard-cycle application when bm = low and the device is in long-word (36-bit) operation. a ? special ? mode has been add- ed however to disable all right port i/os while the chip is active. this i/o disable mode is implemented when size is forced to a logic ? 1 ? while bm is at a logic ? 0 ? . it allows the bus- matched port to support a chip enable ? don ? t care ? sema- phore read/write access similar to that provided on the left port of the device when all byte select (b 0 ? 3 ) control inputs are deselected. the bus size select (size) pin selects either a byte or word data arrangement on the right port when the bus match select (bm) pin is high. a logic ? 1 ? on the size pin when the bm pin is high selects a byte bus (9-bit) data arrangement). a logic ? 0 ? on the size pin when the bm pin is high selects a word bus (18-bit) data arrangement. the level of the bus size select (size) must also be static throughout normal device operation. long-word (36-bit) operation bus match select (bm) and bus size select (size) set to a logic ? 0 ? will enable standard cycle long-word (36-bit) opera- tion. in this mode, the right port ? s i/o operates essentially in an identical fashion as does the left port of the dual-port sram. however no byte select control is available. all 36 bits of the long-word are shifted into and out of the right port ? s i/o buffer stages. all read and write timing parameters may be identical with respect to the two data ports. when the right port is con- figured for a long-word size, word address (wa), and byte address (ba) pins have no application and their inputs are ? don ? t care ? [51] for the external user. word (18-bit) operation word (18-bit) bus sizing operation is enabled when bus match select (bm) is set to a logic ? 1 ? and the bus size select (size) pin is set to a logic ? 0 ? . in this mode, 18 bits of data are ported through i/o 0r ? 17r . the level applied to the word address (wa) pin during word bus size operation determines whether the most-significant or least-significant data bits are ported through the i/o 0r ? 17r pins in an upper word/lower word se- lect fashion (note that when the right port is configured for word size operation, the byte address pin has no application and its input is ? don ? t care ? [51] ). device operation is accomplished by treating the wa pin as an additional address input and using standard cycle address and data setup/hold times. when transferring data in word (18-bit) bus match format, the unused i/o 18r ? 35r pins are three-stated. byte (9-bit) operation byte (9-bit) bus sizing operation is enabled when bus match select (bm) is set to a logic ? 1 ? and the bus size select (size) pin is set to a logic ? 1 ? . in this mode, data is ported through i/o 0r ? 8r in four groups of 9-bit bytes. a particular 9-bit byte group is selected according to the levels applied to the word address (wa) and byte address (ba) input pins. device operation is accomplished by treating the word ad- dress (wa) pin and the byte address (ba) pins as additional address inputs having standard cycle address and data set- up/hold times. when transferring data in byte (9-bit) bus match format, the unused i/o 9r ? 35r pins are three-stated. 9 / ba wa cy7c056v cy7c057v 16k/32kx36 dual port bm size 9 / 9 / 9 / x9, x18, x36 / bus mode x36 / i/os rank wa ba i/o 27r ? 35r upper-msb 1 1 i/o 18r ? 26r lower-msb 1 0 i/o 9r ? 17r upper-msb 0 1 i/o 0r ? 8r lower-msb 0 0 note: 51. even though a logic level applied to a ? don ? t care ? input will not change the logical operation of the dual-port, inputs that are temporarily a ? don ? t care ? (along with unused inputs) must not be allowed to float. they must be forced either high or low.
cy7c056v cy7c057v 20 preliminary ordering information shaded areas contain advance information. document #: 38 ? 00742 ? b speed (ns) ordering code package name package type operating range 10 cy7c056v ? 10ac a144 144-pin thin quad flat pack commercial cy7c056v ? 10bac bb172 172-ball ball grid array (bga) commercial 12 cy7c056v ? 12ac a144 144-pin thin quad flat pack commercial cy7c056v ? 12bac bb172 172-ball ball grid array (bga) commercial 15 cy7c056v ? 15ac a144 144-pin thin quad flat pack commercial cy7c056v ? 15ai a144 144-pin thin quad flat pack industrial cy7c056v ? 15bac bb172 172-ball ball grid array (bga) commercial cy7c056v ? 15bai bb172 172-ball ball grid array (bga) industrial 20 cy7c056v ? 20ac a144 144-pin thin quad flat pack commercial cy7c056v ? 20bac bb172 172-ball ball grid array (bga) commercial speed (ns) ordering code package name package type operating range 10 cy7c057v ? 10ac a144 144-pin thin quad flat pack commercial cy7c057v ? 10bac bb172 172-ball ball grid array (bga) commercial 12 cy7c057v ? 12ac a144 144-pin thin quad flat pack commercial cy7c057v ? 12bac bb172 172-ball ball grid array (bga) commercial 15 cy7c057v ? 15ac a144 144-pin thin quad flat pack commercial cy7c057v ? 15ai a144 144-pin thin quad flat pack industrial cy7c057v ? 15bac bb172 172-ball ball grid array (bga) commercial cy7c057v ? 15bai bb172 172-ball ball grid array (bga) industrial 20 cy7c057v ? 20ac a144 144-pin thin quad flat pack commercial cy7c057v ? 20bac bb172 172-ball ball grid array (bga) commercial
cy7c056v cy7c057v 21 preliminary package diagrams 144-pin plastic thin quad flat pack (tqfp) a144 51-85047-a
cy7c056v cy7c057v preliminary ? cypress semiconductor corporation, 2000 the information contained herein is subject to change without notice. cypress semicon ductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagrams (continued) 172-ball bga bb172 51-85114

▲Up To Search▲

Price & Availability of CY7C056V-10BAC

	To Download CY7C056V-10BAC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .